Third Workshop on
Programmability Issues for Multi-Core Computers
(MULTIPROG)
Held in conjunction with:
the 5th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC)
Pisa, Italy, January 24, 2010
Computer manufacturers have already embarked on the multi-core roadmap, promising to double the number of processors on a chip every other year, and many-cores are on the horizon. This shift to an increasing number of cores and heterogeneous architectures has placed new burdens on the programming community. Until now, software has been developed with a single processor in mind and it needs to be parallelized (and optimized for accelerators such as GPUs) to take advantage of the new breed of multi-/many-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.
The third edition of the MULTIPROG workshop aimed to bring together, and cause fruitful interaction between, researchers interested in programming models and their implementation and in computer architecture with the common interest in advancing our knowledge how to simplify the task of parallelization of software for multi-core platforms. A wide spectrum of issues were central themes for this workshop such as what the future programming models should look like to accelerate software productivity and how it should be implemented at the runtime, the compiler, and the architecture level.
MULTIPROG is intended for quick publication of early results, work-in-progress, etc, and is not intended to prevent later publication of extended papers. We prioritized papers addressing cross-cutting issues and that provide thought-provoking insights into the main themes. All the paperswere published on the workshop informal proceedings. Some papers were selected for a special issue of Transactions on HiPEAC, after a new review process.
Topics of interest
Papers were sought on topics including, but not limited to:
- Multi-core architectures
- Architectural support for compilers/programming models
- Processor (core) architecture and accelerators (GPUs, ...)
- Memory system architecture
- Performance/power issues
- Programming models for multi-core architectures
- Language extensions
- Run-time systems
- Compiler optimizations and techniques
- Tools for discovering and understanding parallelism
- Benchmarking of multi-/many-core architectures
Final program
PDF file with all papers included in the informal proceedings.
| 09:00-10:00 | Keynote session: |
| Making Sense of Transactional Memory Tim Harris, Microsoft Research Cambridge. | |
| 10:00-10:30 | Best Paper |
| Noninvasive concurrency with Java STM | |
| G. Korland (Tel Aviv U.) N. Shavit (Tel Aviv U.), P. Felber (U. of Neuchatel) | |
| 10:30-11:00 | Coffee break |
| 11:00-12:30 | Session 1 |
| Parallelizing Barnes-Hut Method on the Cell BE Architecture | |
| B. Demioz (Bogazici U.), H. Topcuoglu (Marmara U.), M. Kandemir (Pennsylvania State U.), O. Tosun (Bogazici U.) | |
| Expressing Inter-task Dependencies between Parallel Stencil Operations | |
| P. Larsen, S. Karlsson, J. Madsen (Dept. of Informatics, Technical University of Denmark) | |
| A Performance Comparison of some recent Task-based Parallel Programming Models | |
| A. Podobas (KTH), M. Brorsson (KTH and Swedish Institute of Computer Science), K. Faxén (Swedish Institute of Computer Science) | |
| 12:30-14:00 | Lunch |
| 14:00-15:30 | Session2 |
| Handling of shared memory in many-core processors without locks and transactional memory | |
| A. Vajda (Ericsson) | |
| J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors | |
| M. Paolieri (BSC), I. Bonesana (SUPSI), R. Gioiosa (BSC), M. Valero (UPC / BSC) | |
| Building a Java Map-Reduce Framework for Multi-core Architectures | |
| G. Kovoor; J. Singer, M. Lujan (U. of Manchester) |
Organizers
| Eduard Ayguade | UPC/Barcelona Supercomputing Center | Spain | eduard[at]ac.upc.edu |
| Roberto Gioiosa | IBM Research - Watson | USA | rgioios[at]us.ibm.com |
| Per Stenstrom | Chalmers University of Technology | Sweden | pers[at]chalmers.se |
| Osman Unsal | BSC-Microsoft Research Centre | Spain | osman.unsal[at]bsc.es |
Program committee
| Mohammad Ansari | University of Manchester | UK |
| Francois Bodin | CAPS Entreprise | France |
| Mats Brorsson | KTH | Sweden |
| Magnus Ekman | NVIDIA | USA |
| Pascal Felber | University of Neuchatel | Switzerland |
| Maria Garzaran | University of Illinois, Urbana-Champaign | USA |
| Guang Gao | University of Delaware | USA |
| Roberto Giorgi | University of Siena | Italy |
| Tim Harris | Microsoft Research Cambridge | UK |
| Stefanos Kaxiras | University of Patras | Greece |
| Mikel Lujan | University of Manchester | UK |
| Milo Martin | University of Pennsylvania | USA |
| Ami Marowka | Bar-Ilan University | Israel |
| Avi Mendelson | Microsoft | Israel |
| Dimitris Nikolopoulos | FORTH-ICS | Greece |
| Oscar Plata | University of Malaga | Spain |
| Andre Seznec | INRIA/IRISA | France |
| Nir Shavit | Tel Aviv University | Israel |
| Peng Wu | IBM Research Watson | USA |
Webmaster: eduard[at]ac.upc.edu