Second Workshop on
Programmability Issues for Multi-Core Computers
(MULTIPROG)
Held in conjunction with:
the 4th International Conference on
High-Performance and Embedded Architectures and Compilers (HiPEAC)
Paphos, CYPRUS, January 25, 2009
Computer manufacturers have already embarked on the multi-core roadmap, promising to double the number of processors on a chip every other year, and many-cores are on the horizon. This shift to an increasing number of cores has placed new burdens on the programming community. Until now, software has been developed with a single processor in mind and it needs to be parallelized to take advantage of the new breed of multi-/many-core computers. As a result, progress in how to easily harness the computing power of multi-core architectures is in great demand.
This workshop aimed to bring together, and cause fruitful interaction between, researchers interested in programming models and their implementation and in computer architecture with the common interest in advancing our knowledge how to simplify the task of parallelization of software for multi-core platforms. A wide spectrum of issues were central themes for this workshop such as what the future programming models should look like to accelerate software productivity and how they should be implemented at the runtime, the compiler, and the architecture level.
We priorized papers reporting on on-going work that address cross-cutting issues and that provide thought-provoking insights into the main themes. All the papers were published on the workshop informal proceedings.
Topics of interest
Papers were sought on topics including, but not limited to:
- Multi-core architectures
- Architectural support for compilers/programming models
- Processor (core) architecture and accelerators (GPUs, ...)
- Memory system architecture
- Performance/power issues
- Programming models for multi-core architectures
- Language extensions
- Run-time systems
- Compiler optimizations and techniques
- Tools for discovering and understanding parallelism
- Applications for multi-core architectures
- Methodologies
- Benchmarking
Final program
PDF file with all papers included in the informal proceedings.
| 09:15-09:30 | Opening remarks |
| 09:30-10:30 | Keynote session: |
| Georgi Gaydadjiev, Delft University of Technology. SARC - the future scalable heterogeneous architecture and its programing model | |
| 10:30-11:00 | Coffee break |
| 11:00-13:00 | Session 1: Programming Models |
| Comparing Programmability and Scalability of Multicore Parallelization Paradigms with C++ | |
| C. Terboven, C. Schleiden and D. Mey (RWTH Aachen University) | |
| Towards Automatic Profile-Driven Parallelization of Embedded Multimedia Applications | |
| G. Tournavitis and B. Franke (University of Edimburgh) | |
| Investigating Contention Management for Complex Transactional Memory Benchmarks | |
| M. Ansari, C. Kotselidis, M. Lujan, C. Kirkham and I. Watson (University of Manchester) | |
| Profiling Transactional Memory applications on an atomic block basis: A Haskell case study | |
| N. Sonmez (BSC), A. Cristal (BSC), O. S. Unsal (BSC), T. Harris (Microsoft) and M. Valero (BSC) | |
| 13:00-15:00 | Lunch |
| 15:00-16:30 | Session2: Multicore Architecture |
| Power-Efficient Scaling of CMP Directory Coherence | |
| S. Kaxiras, G. Keramidas and I. Oikonomou (University of Patras) | |
| Memory-Communication Model for Low-Latency X-ray Video Processing on Multiple Cores | |
| A. Albers (Eindhoven University of Technology), E. Suijs (Philips Healthcare) and P. With (Eindhoven University of Technology) | |
| A Dual Mesh Tiled CMP | |
| P. Sam, M. Horsnell and I. Watson (University of Manchester) | |
| 16:30-17:00 | Coffee break |
| 17:00-18:30 | Panel Session: |
| How do we make the 10+ million programmers out there productive in the many-core era? [Abstract] Moderator: Per Stenström, Chalmers, Sweden. Panelists: Babak Falsafi, EPFL, Switzerland; Stefanos Kaxiras, University of Patras, Greece; Xavier Martorell, BSC/UPC, Spain; Olivier Temam, INRIA, France; Ian Watson, Manchester University, U.K. |
Organizers
| Eduard Ayguade | Barcelona Supercomputing Center | Spain | eduard[at]ac.upc.edu |
| Roberto Gioiosa | IBM Research - Watson | USA | rgioios[at]us.ibm.com |
| Per Stenstrom | Chalmers University of Technology | Sweden | pers[at]chalmers.se |
| Osman Unsal | Barcelona Supercomputing Center | Spain | osman.unsal[at]bsc.es |
Program commitee
| David Bernstein | IBM Research Lab in Haifa | Israel |
| Mats Brorsson | KTH | Sweden |
| Barbara Chapman | University of Houston | USA |
| Marcelo Cintra | University of Edinburgh | U.K. |
| Magnus Ekman | Sun Microsystems | USA |
| Pascal Felber | University of Neuchatel | Switzerland |
| Christof Fetzer | Dresden University of Technology | Germany |
| Matthew I. Frank | Univeristy of Illinois, Urbana-Chhampaign | USA |
| Guang Gao | University of Delaware | USA |
| Roberto Giorgi | University of Siena | Italy |
| Erik Hagersten | Uppsala University | Sweden |
| Mark Harris | Nvidia | Australia |
| Jay P. Hoeflinger | Intel | USA |
| Haoquiang Jin | NASA Ames | USA |
| Stefanos Kaxiras | University of Patras | Greece |
| Mikel Lujan | University of Manchester | UK |
| Ami Marowka | Shenkar College of Engineering and Design | Israel |
| Avi Mendelson | Intel | USA |
| Dieter an Mey | RWTH, Aachen | Germany |
| Andre' Seznec | IRISA | France |
| Peng Wu | IBM Watson Research | USA |
Webmaster: eduard.ayguade[at]bsc.es